1. Field of the Invention
The present invention generally relates to parallel processor architectures and, more specifically, to cooperative thread array granularity context switch during trap handling.
2. Description of the Related Art
In computer architecture, a trapping instruction is a type of instruction that interrupts a currently running program. Interruptions of a program may occur for various reasons. Examples of ordinary trap occurrences could include a system call for more information, or a pause in which the computer is instructed to wait for user input (e.g., pressing a key on a keyboard). Examples of trap occurrences in response to an error could include attempts to perform an illegal computer operation, such as dividing by zero, or accessing an invalid memory location. In addition, trapping instructions may be manually inserted by a programmer for debugging purposes.
When a trapping instruction is encountered, a dedicated program known as a trap handling routine is executed, (e.g., by causing the program counter to point to a trap handling routine, also known as a trap handler). A context switch is typically performed when executing a trap handling routine. In general, context switching describes the computing process of storing and restoring the state of a processing unit so that execution of the running program can be resumed from the point of interruption at a later time. Typically, context switching is computationally expensive.
In a parallel processing system, in which multiple threads are processed simultaneously across different execution units as a single logical unit, known as a cooperative thread array, a trap encountered in a single thread (hereinafter referred to as a “trapping thread”) causes a context switch of all executing threads. Such an occurrence is not desirable because context switches in executing threads other than that of the trapping thread cause computer resources to be consumed unnecessarily and a slowdown in execution of non-trapping threads.
Accordingly, what is needed in the art is a trap handling routine that operates efficiently in parallel processors.